1. Field of the Invention
The present invention relates to a method of forming a metal via in a semiconductor integrated circuit (IC), and, more particularly, to a method of forming a metal via in a semiconductor integrated circuit by utilizing an intermediate mask layer to etch the metal via for improving the step coverage of a metal contact layer.
2. Technical Background
A conventional method of forming a metal via in a semiconductor integrated circuit is shown in FIGS. 1a to 1e. The semiconductor integrated circuit includes a semiconductor substrate (not shown), a metal layer 120, and a dielectric layer 140. The dielectric layer 140 has a first dielectric such as silicon oxide layer 1420 which is formed by plasma enhanced chemical vapor deposition (PECVD), a second dielectric such as spin-on glass (SOG) 1440, and a third dielectric such as second silicon oxide layer 1460 which is also formed by PECVD. The conventional method of forming a metal via includes the steps as follows:
(1) Coating a photoresist layer 160 on the dielectric layer 140, and forming an opening 1620 at a predetermined position by conventional lithography techniques, as shown in FIG. 1a.
(2) Forming a metal via 10 by dry etching using the photoresist 160 as a mask as shown in FIG. 1b. Then, as illustrated in FIG. 1c, the photoresist 160 is removed by plasma or solvent. Alternatively, and as shown in FIG. 1d, the metal via 10 may be formed according to conventional wet by dry etching processes. In wet by dry etching processes a wet etch is used first to isotropically etch the top portion of the via, and then a dry etch is used to anisotropically etch the remainder of the via.
In the production of very large scale integrated circuits (VLSIs), flatness between multiple metal layers is usually maintained by using SOG. Since SOG can not be cured at sufficiently high temperature in order to achieve the same quality as PECVD SiO.sub.2 while metal (Aluminum) is present, unwanted damage occurs on the sidewalls of the metal via 10 during removal of the photoresist by plasma or solvent. As shown in FIG. 1e, damages in the via associated with SOG structure such as poor step coverage, or poor surface property for a later formed metal layer 180 results in a contact failure in the metal via 10. The effect of via damage is even worse when siloxane type of SOG is used.
Another problem of the conventional method is deformation of the metal via 10. Since the dielectric layer 140 is transparent to ultraviolet light and the metal layer 120 is highly reflective, the opening 1620 is enlarged during exposure due to reflection of ultraviolet light in the dielectric layer 140.
There are other problems in the conventional method. Since the dielectric layer is to be etched to form the opening 1620, the thickness of the photoresist 160 is usually 20 to 30 k.ANG.. If the thickness of the photoresist 160 can be reduced, the photoresist is easier to develop. Furthermore, a reduction in thickness of the photoresist 160 reduces the problem of depth of focus in alignment and results in cost savings because less photoresist 160 is used.